In recent years, techniques have been proposed in which MOS transistors are used for muting input and output in the input/output interfaces of audio amplifiers or the like to which positive and negative signals are outputted.
However, when a MOS transistor for muting is turned off, input/output signals largely fluctuating to the negative side may turn on a parasitic diode between the back gate and the drain or source of the MOS transistor. Thus the input/output signals are clamped and distortion occurs on the signals.
In order to avoid the clamping of input/output signals, Japanese Patent Laid-Open No. 2002-111446 proposes a known technique of applying a negative voltage to the back gate of a MOS transistor.
A mute circuit disclosed in Japanese Patent Laid-Open No. 2002-111446 comprises an amplifier and an Nch (channel) MOS transistor for muting.
The amplifier has an input connected to an input terminal and an output connected to an output terminal via a first resistor, and the amplifier outputs positive and negative signals in a state in which the center level of the output signal is set at the ground potential. The NchMOS transistor has a drain connected to a junction point between the first resistor and the output terminal and a source connected to the ground potential. A second resistor is connected between the gate and the back gate of the transistor. In this mute circuit, a parasitic diode appears between the drain and the back gate of the NchMOS transistor.
In this configuration, a power supply potential is applied to the gate of the NchMOS transistor and the back gate of the NchMOS transistor through the second resistor to turn on the NchMOS transistor. At this time, a signal inputted to the input terminal is muted on the output of the amplifier in accordance with the ratio between the first resistor and the ON resistance of the NchMOS transistor. Further, a negative potential equivalent to the power supply potential is applied to the gate of the NchMOS transistor and the back gate of the NchMOS transistor through the second resistor to turn off the NchMOS transistor. At this time, the signal having been inputted to the input terminal is driven by the amplifier without being muted, and then is outputted to the output terminal. The negative potential is applied to the back gate of the NchMOS transistor when muting is turned off, and the output signal does not fall below the back gate voltage of the NchMOS transistor when the output signal is outputted to the negative side. Thus the parasitic diode between the drain and the back gate of the NchMOS transistor is not turned on, so that the output signal is not clamped when muting is turned off, preventing distortion on the output signal.
However, when muting is turned off in this known mute circuit, the output signal outputted to the maximum to the positive side may maximize a voltage difference between the drain and the back gate of the NchMOS transistor and the voltage difference may be equal to a voltage difference between the power supply potential and the negative potential. For this reason, the breakdown voltage of the NchMOS transistor has to be equal to or higher than the voltage difference between the power supply potential and the negative potential. For example, when the power supply potential is 3 V and the negative potential is (−3) V, the maximum voltage of about 6 V may be applied between the drain and the back gate of the NchMOS transistor when muting is turned off, so that the NchMOS transistor for muting requires the breakdown voltage of 6 V or higher. Conversely, when the breakdown voltage of the NchMOS transistor is 6 V or higher, the power supply potential is limited within 3 V and the negative potential is limited within (−3) V. In this way, the power supply voltage range on the positive side and the negative side is limited within one half of the breakdown voltage of the NchMOS transistor for muting.